1. Field of the Invention
The present invention generally relates to a semiconductor apparatus for charging a capacitor, and more particularly, to a semiconductor apparatus in which multiple parallel monitor circuits are integrated for evenly charging multiple electric double layer capacitors connected in series.
2. Description of the Related Art
An electric double layer capacitor can be charged more quickly than a secondary battery is. Additionally, an electric double layer capacitor can store more energy than a secondary battery can. Since the rated voltage of an electric double layer capacitor is about 2.7 V, if a higher voltage is required, multiple capacitors connected in series are used.
When multiple capacitors connected in series are charged, uneven charging of the capacitors may occur due to the diversity of capacitance of each capacitor, self-charging, and self-discharging.
A circuit called “parallel monitor” for evenly charging multiple capacitors is used to solve the above problem.
FIG. 4 is a circuit diagram showing a portion of a parallel monitor circuit disclosed in Japanese Patent Laid-Open Application No. 2000-050495.
The same parallel monitor as shown in FIG. 4 is provided to each one of multiple capacitors connected in series. The parallel monitor is described below with reference to FIG. 4.
The parallel monitor circuit shown in FIG. 4 includes reference voltages Vr1 and Vr2, a comparator circuit CMP for comparing the voltage of a capacitor C1 with the reference voltage Vr1 or Vr2, switches S1 and S2 for switching the reference voltages Vr1 and Vr2, a transistor Tr1 for bypassing the charge current that flows into the capacitor C1, and a switch control circuit for controlling the switches S1 and S2 in accordance with the output of the comparator circuit CMP.
The reference voltage Vr1 is set at 3 V which is the full charge voltage of the capacitor C1, and the reference voltage Vr2 is set at 0.8 V which is less than the full charge voltage of the capacitor C1. At the initial stage of charge, the switch S1 is connected to the reference voltage Vr2. When the voltage of the capacitor C1 increases up to 0.8 V, the output of the comparator circuit CMP is inverted, and turns on the transistor Tr1. When the transistor Tr1 is turned on, the capacitor C1 is discharged, and the time constant of the discharge is determined by the resistance component of the circuit including the transistor Tr1. The switch control circuit monitors the outputs of all comparator circuits CMP. While the capacitor C1 is discharged, if the charge voltage of another capacitor increases up to the reference voltage 0.8 V, the switch S1 is switched to the reference voltage Vr1, and bypass mode is discharged. The capacitors are charged up to the full charge voltage 3 V.
As described above, the quantity of the parallel monitor circuits required is equal to the number of capacitors that are connected in series. The scale of the entire parallel monitor circuits become large. However, the conventional parallel monitor circuits have not integrated in a semiconductor apparatus but assembled using discrete components. The scale of the conventional parallel monitor circuits are large, and their cost is high. The integration of the parallel monitor circuits are desired to solve the above problem.
However, the quantity of capacitors connected in series depends on their application. It is not practical to design and manufacture a semiconductor apparatus in which the suitable number of parallel monitor circuits are integrated for each application.
It is also not advantageous to make a semiconductor apparatus in which only one parallel monitor circuit is integrated.
To solve above problem, five through ten parallel monitor circuits are integrated in a semiconductor apparatus IC1 (five in the case of FIG. 1) as shown in FIG. 1. If there are capacitors more than the parallel monitor circuits integrated in one semiconductor apparatus that are to be charged, the semiconductor apparatuses are cascaded as many as necessary. According to the above arrangements, the reasonable number of parallel monitor circuits can be integrated in a semiconductor apparatus so as to increase the efficiency of integration and consequently to reduce the cost of the parallel monitor circuits.
Even in the case in which multiple parallel monitor circuits are integrated in one semiconductor apparatus (hereinafter referred to as a monitor IC), the control circuit for monitoring the output of the comparator circuit CMP and for switching the reference voltages is configured by a CPU, for example, and the control circuit is usually separate from the semiconductor apparatus as shown in FIG. 4.
In the case of multiple monitor ICs are cascaded (two in the case of FIG. 1), the voltage applied to the power supply voltages Vdd (plus) and Vss (minus) of each monitor IC may be different. As a result, the voltage level of signal lines for exchanging signals with the control circuit may differ for each monitor IC. It is impossible to directly connect the control circuit and all monitor ICs.
This problem can be solved by a technique in which wiring is made between the control circuit and the monitor IC1, the minus power supply voltage Vss of which is common to the minus power supply voltage Vss of the control circuit, and the monitor IC1 shifts the voltage level of the control signal, and the control signal line is connected from the terminal of the monitor IC1 to the terminal of the monitor IC2 as shown in FIG. 1. This connection technique is referred to as daisy chain.
However, as apparent from FIG. 1, since the plus power supply voltage Vdd of the monitor IC1 is the minus power supply voltage Vss of the monitor IC2, voltage between the minus power supply voltage Vss of the monitor IC1 and the plus power supply voltage Vdd of the monitor IC2 is applied to terminals CON1 through CON12 that connects the monitor IC1 and the monitor IC2. As a result, the monitor IC1 and monitor IC2 need to have withstanding voltage twice as high as the power supply voltage of the monitor IC in the case in which one monitor IC charges one capacitor. Since a high withstanding voltage transistor is larger than a low withstanding voltage transistor, the chip size and cost of the monitor IC is increased.